Cyclone 10 LP SERDES max data rate

Question

Greetings. Could someone point me to which document/section would describe the max data rate for the SERDES on a Cyclone 10 LP? I am having trouble locating that value.

yuanli_s_intel · Answer

Hi Ross,Are you saying the SERDES internal logic or the LVDS I/O? Thank You.

rpett4 · Answer

Both. I need a high speed parallel to serial converter (SERDES) which will output over LVDS I/O.

yuanli_s_intel · Answer

You may refer to datasheet at page below for more information about it:https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51002.pdf (Page 29)

Forum Discussion

Cyclone 10 LP SERDES max data rate

3 Replies

Recent Discussions

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work

PCIe Root Complex on DK-A5E013BM16AEA