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ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
7 months ago
Solved

Cyclone 10 LP pin configuration

Hi

My FPGA model is: Cyclone 10 LP 10CL120YF484I7G.

Bank 4 pin AA12 and AB12 are dedicated clock pin. I input crystal oscillator which is 1.8V single-ended clock to AA12, and input negative differential signal to AB12. The questions are:

1) is bank 4 of Cyclone 10 LP able to be configured as 1.8V single and 1.8V differential pin?

2) in Pin Planner, what is the default LVDS voltage suppose the reference voltage of Bank 4 is 1.8V?

3) AA12 is connected to single-ended 1.8V crystal oscillator, and AB12 is connected negative differential signal. Does this work?

https://www.intel.com/content/www/us/en/docs/programmable/683137/current/clock-and-pll-pins.htmlConvert Programming Files

Fpga Devkit
  • FvM's avatar
    FvM
    7 months ago

    Hi,
    LVDS IO standard is supported for 2.5V banks only. In 1.8 V banks, you can use differential SSTL-18 I/O standard, but it doesn't use true differential receivers and needs bank VREF to be connected to 0.5 × VCCIO:

    The Differential SSTL input standard is supported on the GCLK pins only, treating
    differential inputs as two single-ended SSTL and only decoding one of them.

    The Differential SSTL I/O standard requires two differential inputs with an external
    reference voltage (VREF) and an external termination voltage (VTT) of 0.5 × VCCIO to
    which termination resistors are connected.
    (Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook 5.8.2.5. Differential SSTL I/O Standard in Intel Cyclone 10 LP Devices)

    Single ended clock inputs are supported with all bank voltages, also 1.8V. Both AA12 and AB12 can be used as single ended clock inputs. A differential clock input uses both pins of a differential pair. Respectively this can't work:

    3) AA12 is connected to single-ended 1.8V crystal oscillator, and AB12 is connected negative differential signal. Does this work?

    Regards
    Frank

3 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Hi,
    LVDS IO standard is supported for 2.5V banks only. In 1.8 V banks, you can use differential SSTL-18 I/O standard, but it doesn't use true differential receivers and needs bank VREF to be connected to 0.5 × VCCIO:

    The Differential SSTL input standard is supported on the GCLK pins only, treating
    differential inputs as two single-ended SSTL and only decoding one of them.

    The Differential SSTL I/O standard requires two differential inputs with an external
    reference voltage (VREF) and an external termination voltage (VTT) of 0.5 × VCCIO to
    which termination resistors are connected.
    (Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook 5.8.2.5. Differential SSTL I/O Standard in Intel Cyclone 10 LP Devices)

    Single ended clock inputs are supported with all bank voltages, also 1.8V. Both AA12 and AB12 can be used as single ended clock inputs. A differential clock input uses both pins of a differential pair. Respectively this can't work:

    3) AA12 is connected to single-ended 1.8V crystal oscillator, and AB12 is connected negative differential signal. Does this work?

    Regards
    Frank

  • ZhiqiangLiang's avatar
    ZhiqiangLiang
    Icon for Occasional Contributor rankOccasional Contributor
    7 months ago

    @FvM

    My FPGA is connected to ADC which output only 1.8V differential signal.

    The main problem is: ADC output 1.8V differential signal can't be configured.

    The questions are:

    1) Bank reference voltage is supplied by 2.5V. FPGA pins are constrained to LVDS which is real 2.5V, but the input from ADC is 1.8V differential. Does this work?

    2) Bank reference voltage is supplied by 1.8V. FPGA pins are constrained to LVDS which is fake 2.5V, but the input from ADC is 1.8V differential. Does this work?

    3) if I would like to make the 1.8V differential signal from ADC be connected LVDS of FPGA, what bank voltage should be connected?