ZhiqiangLiang
Occasional Contributor
Occasional ContributorCyclone 10 LP pin configuration
Hi My FPGA model is: Cyclone 10 LP 10CL120YF484I7G. Bank 4 pin AA12 and AB12 are dedicated clock pin. I input crystal oscillator which is 1.8V single-ended clock to AA12, and input negative diffe...
Hi,
LVDS IO standard is supported for 2.5V banks only. In 1.8 V banks, you can use differential SSTL-18 I/O standard, but it doesn't use true differential receivers and needs bank VREF to be connected to 0.5 × VCCIO:
The Differential SSTL input standard is supported on the GCLK pins only, treating
differential inputs as two single-ended SSTL and only decoding one of them.
The Differential SSTL I/O standard requires two differential inputs with an external
reference voltage (VREF) and an external termination voltage (VTT) of 0.5 × VCCIO to
which termination resistors are connected.
(Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook 5.8.2.5. Differential SSTL I/O Standard in Intel Cyclone 10 LP Devices)Single ended clock inputs are supported with all bank voltages, also 1.8V. Both AA12 and AB12 can be used as single ended clock inputs. A differential clock input uses both pins of a differential pair. Respectively this can't work:
3) AA12 is connected to single-ended 1.8V crystal oscillator, and AB12 is connected negative differential signal. Does this work?Regards
Frank
