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OlegT's avatar
OlegT
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Cyclone 10 GX FPGA Development Kit - PCIe AvalonMM-DMA example

Hello. I use AN829 as starting point of my design. In Platform Builder I see, that PCIe hip is connected to DDR3 emif via avalon MM bus. Both components use different clock sources, but they ar...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    4 years ago

    Hi Oleg,

    Thanks for your patience while I was checking the design.

    If you refer to the Platform Designer: Interconnect Requirements, there are some settings that allow the software to automatically insert the clock crossing adapters and add pipeline stages to the Platform Designer interconnect when you generate a system.

    In our case, the clock crossing adapter type is set to FIFO and maximum pipeline stages is set to 4.

    Thanks

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY