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LGonz14's avatar
LGonz14
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7 years ago

Cyclone 10 GX Development Kit USB3.1 HD3SS3220 DRP Controller attached status?

To whom it may concern,

I'm trying to verify connectivity and/or attached status of the USB3.1 HD3SS3220 DRP controller via I2C from the FPGA but it seems the device always reports being unattached and in DRP mode even when it is connected to a USB3.0 port using a USB3.1 gen1 compatible cable. I poke registers 0x08 and 0x09 to verify for attached and cable active states. Is there a procedure for properly configuring this device? Also, is there a device driver available for this controller to verify connectivity via software instead?

regards,

Luis Gonzalez

Beckman Coulter, Inc.

5 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    7 years ago
    Hi Luis, As I understand it, you have some inquiries related to the TI HD3SS3220 DRP controller on the C10GX devkit. For your information, generally we would address FPGA specific in this Forum but I will try my best to further assist you on this to my best knowledge. Sorry for the inconvenience. As I understand it, you are trying to read the controller's register at 0x08 and 0x09 to check on the cable connection status but the values indicate no connection even with cable present. Just would like to check with you if you would me to further engage our I2C expert to help checking if there is any anomaly with I2C access methodology from FPGA? As I check through the HD3SS3220 datasheet, I believe the controller has been configured properly as the configuration seems to be through hard wire connection on devkit ie DRP mode selection. Regarding the device driver, just wonder if you are referring to FPGA software to access the controller? Or if you are referring to a software from TI to access the controller? If you are referring to FPGA software, I am not aware of any specific software on this. For TI software, it would be great if you could try to consult TI to see if they might have any insight. Just would like to check with you, apart from the status reading anomaly, is the USB 3.1 interface function as expected? Please let me know if there is any concern. Thank you. Best regards, Chee Pin
    • LGonz14's avatar
      LGonz14
      Icon for New Contributor rankNew Contributor
      7 years ago
      Hi Chee, Thank you so much for your prompt reply. Yes, I’m having issues determining the current state of the HD3SS3220 USB 3.1 DRP controller from the FPGA via the i2c protocol. The controller reports being unattached and in DRP mode even when it is physically connected to a USB 3.0 port on a HOST PC. The Host PC doesn’t even try to enumerate the device because apparently the polling phase of the protocol never seems to occur. Therefore, I cannot at this time say for sure that the USB 3.1 interface function is working as it should. I am, however, communicating with TI regarding this issue and they are trying to assist me the best they can. TI has made some hardware change recommendations and I’m trying to make those changes to see if I can make this controller behave the way it should. By device driver, I was referring to OS software that can communicate to the controller to be able to detect its current state. By the way, is there a USB 3.1 reference design for this Cyclone 10 GX FPGA dev kit? Luis A. Gonzalez R&D Department Staff Sr. Electrical Engineer (DSP/FPGA) Beckman & Coulter, Inc. 11800 SW 147th Ave Miami, FL 33196 Tel: (305) 380-3787 [cid:image002.jpg@01D2125B.BDE54990]
  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    7 years ago
    Hi Luis, Sorry for the delay. Glad to hear that you have managed to get in touch with TI on their USB3.1 controller part for further assistance. Regarding the USB 3.1 reference design for C10GX devkit, for your information, as I search through our web, I found that there is a USB 3.1 Gen2 device controller IP provided by our Design Partner which was verified on C10GX devkit at the following link: https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/system-level-solutions--inc-/ip/embedded-usb-3-1-gen-2-device-controller--eusb31sf-.html You may contact our 3rd party design partner if you are interested to know more about this IP. Please let me know if there is any concern. Thank you very much. Best regards, Chee Pin
  • LGonz14's avatar
    LGonz14
    Icon for New Contributor rankNew Contributor
    7 years ago

    ​Hi Chee,

    No worries!

    Will this IP core replace the USB HD3SS3220 DRP Controller or no?

    Best regards,

    Luis Gonzalez

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    7 years ago
    Hi Luis, Regarding your latest inquiries, sorry as I have no visibility into the USB Gen2 device controller IP provided by our Design Partner and could not really comment further. It would be great if you could get in touch with our Design Partner to seek further clarification on their IP. Sorry for the inconvenience. Best regards, Chee Pin