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Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
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2 years ago

Cyclone 10 GX dev kit, which signal can I use to reset a NIOS?

I've had a look at the Cyclone 10 GX dev kit user manual and schematics but it's not clear if the board provides a signal to the C10 that will drive the NIOS platform reset input correctly. Any sugge...
Fpga Devkit
wwanalim_intel's avatar
wwanalim_intel
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2 years ago

I am sorry for the picture above. Below I reattached the picture.

You can enable Include cpu_resetrequest, and use a PIO IP as input into cpu_resetrequest.

 

Or, with the connection below made, use the debug module to reset the core only.

If the same signal is connected to other IP's reset, you can extend to full system reset.

  • Oliver_I_Sedlacek's avatar
    Oliver_I_Sedlacek
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    2 years ago

    This seems to be a way to add more reset (sink) inputs. I'm looking for a reset source to drive the reset input after FPGA configuration.