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PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Cyclone® 10 GX Avalon streaming Hard IP for PCIe* Design Example

I am building this design example. I have two problems: ONE: reference to file in modelsim.tcl do msim_setup.tcl # ** Error: couldn't read file "./../common/./../../../../pcie_example_design...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Pieter,


I don't understand how you specify C10. Ok, now let's assume you generate the example design using Arria 10 variant. Then after that how you specify C10?

Also, I notice there are some folder hierarchy changed in newer version compare to 18.0. May you can give a try on newer quartus version like 20.1/2.

Anyway, from my side I can run the simulation successfully. I just generate the ED using C10 variant, and just follow the normal flow to run the simulation without changing anything including "specify new device".


Thanks


  • PVanL's avatar
    PVanL
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi BoonT, i was away for a few days. I have no idea about a C10. I work with the A10. How do you get the C10? I am using the document UG-20234 | 2019.09.19 with Quartus 18.0.

    What I want to do is: Have a board in the server, send ethernet from server over PCI to ethernet application on FPGA, via transceiver on Cyclone10GX, and back again to the other transceiver on the cyclone10gX, ethernet stack, MAC, PCIexpress, back into the server, and compare if send and received match. Are these the correct settings:

    I specified: ( i only touched the first three settings 1, 2, 3)

    1. Interface view: standalone
    2. Example Design: PIO / with Arria 10 GX Development board (there is no Cyclone10GX board, although it does exist, i am told this Arria 10 GX based design also maps onto the Cyclone 10GX development board)
    3. System Settings:
      * App i/f: Avalon-ST
      * Hard IP mode: Gen2x4 / 128 bit / 125 HMz
      * Port type: Native end point
      * RF buffer: Balance
      * RX Buffer completion credits: Header 112, Data 440
    4. PCIe capabilities: 128 byte/32 tags/NONE timeout/disable completion timeout
    5. "configuration, debug and exentio Options":None of hte options under are marked
    6. PHY characteristics: Gen2 tx de-emphasis: 6dB\
    7. Avalon ST stting: "enable Avalon-ST reset output port
    8. Base Address: Only BAR0: 64 bit prefetchable memory/ 64 kByte - 16 bits