I have tried to generate code using SOPC Builder, but the code it has generated for flash is different from other devices.
For devices like SRAM and SDRAM, It has generated controller code, but for Flash it is not generating controller code, instead it has code which works itself as FLASH, code functions as flash (DUMMY FLASH). That code doesnt connect with hardware flash, but inside code it define memory array which saves data and work as flash memory.
This is code generated by SOPC for FLASH
====>>main module is in the bottom // turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cfi_flash_0_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 7: 0] q;
input [ 7: 0] data;
input [ 20: 0] rdaddress;
input rdclken;
input [ 20: 0] wraddress;
input wrclock;
input wren;
reg [ 7: 0] mem_array [2097151: 0];
wire [ 7: 0] q;
reg [ 20: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
if (1)
read_address <= rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("cfi_flash_0.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data; ///
memory array end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// if (1)
// read_address <= rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "cfi_flash_0.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 21,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//main module module flash_MAIN (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
)
;
inout [ 7: 0] data;
input [ 20: 0] address;
//address is input which should be output for controller input read_n;
input select_n;
input write_n;
wire [ 7: 0] data;
wire [ 7: 0] data_0;
wire [ 7: 0] logic_vector_gasket;
wire [ 7: 0] q_0;
//s1, which is an e_ptf_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign logic_vector_gasket = data;
assign data_0 = logic_vector_gasket[7 : 0];
//cfi_flash_0_lane0, which is an e_ram
cfi_flash_0_lane0_module cfi_flash_0_lane0
(
.data (data_0),
.q (q_0),
.rdaddress (address),
.rdclken (1'b1),
.wraddress (address),
.wrclock (write_n),
.wren (~select_n)
);
assign data = (~select_n & ~read_n)? q_0: {8{1'bz}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
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