New ContributorHi I am new to this site. I have a cyclone V and am trying to drive both a LCD and VGA using the CVO out. I have set the CVO to separate syncs. The LCD (640x480) kind of works, DE signal to LCD sync structure is incorrect and the separate H and Vsync outputs are inactive.
Is there anything in the CV GUI that could keep separate sync option off?
Thanks.
Regular ContributorHi,
As I understand it, you have some inquiries related to the CV CVO with separate sync. To facilitate further debugging, just would like to check with you on the following:
Please let me know if there is any concern. Thank you.
New ContributorHi,
where can I find an example of TPG->CVO to simulate?
Regular ContributorHi,
Regarding your inquiry on the simulation example, for your information, you can create a simple Qsys system with TPG -> CVO with your targeted configuration. Then go to Generate -> Generate Testbench System. You can then further customize the test bench ie connecting the clocks according and the run through Modelsim simulation.
Please let me know if there is any concern. Thank you.
New ContributorHi,
I am almost there. Generated the TB and successfully compiled but couldn't simulate.
here are some of the errors:
vsim work.TPG_CVO
# Start time: 14:02:16 on Oct 16,2020
# Loading work.TPG_CVO
# Loading work.TPG_CVO_alt_vip_cl_tpg_0
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v(72): Instantiation of 'alt_vip_video_output_bridge' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO/alt_vip_cl_tpg_0 File: C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# Loading sv_std.std
# Loading work.TPG_CVO_alt_vip_cl_tpg_0_scheduler
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv(75): Instantiation of 'alt_vip_tpg_multi_scheduler' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO/alt_vip_cl_tpg_0/scheduler File: C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v(124): Instantiation of 'alt_vip_tpg_bars_alg_core' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO/alt_vip_cl_tpg_0 File: C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# Loading work.alt_vipitc131_IS2Vid
# Loading work.alt_vipitc131_common_sync
# Loading work.alt_vipitc131_common_trigger_sync
# Loading work.alt_vipitc131_IS2Vid_control
# Loading work.alt_vipitc131_IS2Vid_mode_banks
# Loading work.alt_vipitc131_IS2Vid_calculate_mode
# Loading work.alt_vipitc131_common_generic_count
# Loading work.alt_vipitc131_common_fifo
# Loading work.alt_vipitc131_IS2Vid_statemachine
# Error loading design
# End time: 14:02:16 on Oct 16,2020, Elapsed time: 0:00:00
# Errors: 3, Warnings: 0
vsim work.TPG_CVO_tb
# vsim work.TPG_CVO_tb
# Start time: 14:03:09 on Oct 16,2020
# Loading work.TPG_CVO_tb
# Loading work.TPG_CVO
# Loading work.TPG_CVO_alt_vip_cl_tpg_0
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v(72): Instantiation of 'alt_vip_video_output_bridge' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb/tpg_cvo_inst/alt_vip_cl_tpg_0 File: C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# Loading sv_std.std
# Loading work.TPG_CVO_alt_vip_cl_tpg_0_scheduler
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv(75): Instantiation of 'alt_vip_tpg_multi_scheduler' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb/tpg_cvo_inst/alt_vip_cl_tpg_0/scheduler File: C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0_scheduler.sv
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v(124): Instantiation of 'alt_vip_tpg_bars_alg_core' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb/tpg_cvo_inst/alt_vip_cl_tpg_0 File: C:/NDT/520/FPGA/TPG_CVO/TPG_CVO/synthesis/submodules/TPG_CVO_alt_vip_cl_tpg_0.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# Loading work.alt_vipitc131_IS2Vid
# Loading work.alt_vipitc131_common_sync
# Loading work.alt_vipitc131_common_trigger_sync
# Loading work.alt_vipitc131_IS2Vid_control
# Loading work.alt_vipitc131_IS2Vid_mode_banks
# Loading work.alt_vipitc131_IS2Vid_calculate_mode
# Loading work.alt_vipitc131_common_generic_count
# Loading work.alt_vipitc131_common_fifo
# Loading work.alt_vipitc131_IS2Vid_statemachine
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(81): Instantiation of 'altera_avalon_st_sink_bfm' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(97): Instantiation of 'altera_avalon_clock_source' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(104): Instantiation of 'altera_avalon_reset_source' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(109): Instantiation of 'altera_conduit_bfm' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(136): Instantiation of 'altera_avalon_st_source_bfm' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(152): Instantiation of 'altera_avalon_clock_source' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(159): Instantiation of 'altera_avalon_reset_source' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(167): Instantiation of 'altera_avalon_clock_source' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v(174): Instantiation of 'altera_avalon_reset_source' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /TPG_CVO_tb File: C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work/TPG_CVO_tb.v
# Searched libraries:
# C:/NDT/520/FPGA/TPG_CVO/simulation/modelsim/rtl_work
# Error loading design
# End time: 14:03:09 on Oct 16,2020, Elapsed time: 0:00:00
# Errors: 12, Warnings: 0
New ContributorHi,
Still having problems. Tried to simulate and here is the latest error list.
