Forum Discussion
New Membercurrently evaluating FPGA solutions
Regular ContributorHi,
As I understand it, you are evaluating the suitable FPGA for your JESD204C application. Can I check with you if you are aware of your local Altera Sales/Field team? If not, feel free to let me know your region and I will reach out to our Sales/Field team to get in touch with you on the suitable FPGA solution for your project.
For your information, the Arria 10 does not support in-house JESD204C IP. Instead, it is supported through third party IP. For example: A third-party JESD204C Transmitter and Receiver IP from Logic Fruit Global Technologies is available in Production status, supporting Arria 10 SX FPGA, Arria 10 GT FPGA, and Arria V GZ FPGA. JESD204C TRANSMITTER AND RECEIVER IP This IP offers better DC balance, clock recovery, and data alignment compared to JESD204B. JESD204C TRANSMITTER AND RECEIVER IP The bit overhead is 3.125%, which is much smaller than JESD204B (~25%). JESD204C TRANSMITTER AND RECEIVER IP Note this is a partner IP, not Altera's own first-party JESD204C core.
Please let me know if there is any inquiry. Thank you.
sudip_parasThank you for the clarification regarding JESD204C support on the Arria 10 FPGA family and for sharing the details of the third-party JESD204C IP from Logic Fruit Global Technologies.
We are based in India and would appreciate it if you could connect us with the relevant Altera Sales/Field team to discuss a suitable FPGA solution for our application.
In addition to JESD204C, could you please also provide information regarding the availability of JESD204B IP for Arria 10 SoC FPGA GX270- 10AX027? Specifically, we would appreciate clarification on the following points:
- Does Altera provide a native JESD204B IP core for the Arria 10 SoC FPGA family?
- If available, which Arria 10 variants and Quartus Prime versions are supported?
- Is the JESD204B IP included with the relevant Quartus Prime edition, or does it require a separate license?
- Are there any official reference designs or application examples demonstrating JESD204B integration with the Analog Devices ADRV9029 transceiver on an Arria 10 SoC platform?
- If JESD204B support is provided through third-party IP, could you please share the recommended IP vendor and relevant technical documentation?
Our application requires a 16 MHz instantaneous RX bandwidth with four RX and four TX channels in the 4.4–4.95 GHz frequency range. We are evaluating the most suitable FPGA platform for interfacing with the ADRV9029 and would like to understand the technical feasibility, IP availability, licensing requirements, and overall development effort.
We look forward to your recommendations and assistance in connecting with the appropriate technical team.
Thank you for your support.
Best regards,
Sudip -Contact Email: [email protected]
PARAS Defence and Space Technologies
India- CheepinC_altera
Hi Sudip,
Thanks for your update. For your information, I have notified our Sales & Field team in India to get in touch with you.
Regarding your latest inquiries, let me address each point directly based on the available technical documentation:
1. Native JESD204B IP for Arria 10 (including SoC variants)
Yes, we support in-house JESD204B IP in Arria 10. The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) devices AN 810: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report , and Altera provides a design example of the JESD204B Intel FPGA IP targeting Arria 10 devices. JESD204B Arria 10 FPGA IP Design Example User GuideThe JESD204B IP is a high-speed point-to-point serial interface for DAC or ADC converters to transfer data to FPGA devices, running at a maximum data rate of 17.4 Gbps. About the JESD204B IP This is Altera's own native IP — not a third-party solution.
2. Quartus Prime Version and Arria 10 Variants
The JESD204B IP is still supported in the latest Quartus Pro version.
3. Licensing
The IP support evaluation mode which allows you to evaluate the IP core in simulation and hardware, before deciding to purchase a full production IP core license. The ordering code for the JESD204B IP is IPS-JESD204. Release Information
4. Reference Design for ADRV9029 on Arria 10 SoC
- There seems to be a documented reference design which should be applicable to your scenario. You may refer to the AN 934: Using Flexible Radio Platform with Arria 10 FPGA and ADI ADRV9029 Sub6G EBZ Board for further details.
Please let me know if there is any inquiry. Thank you.
