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mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
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Critical Warning while generating SOF file for CXLtype 3 example design

Hi, I am getting below Critical Warning while generating SOF file for the example design of CXL IP type 3 with DDR4 controller for Agilex-7 board (DK-DEV-AGI027-RA). "Message ID :- 24567 The desi...
Fpga Devkit
  • FvM's avatar
    FvM
    1 year ago

    Hi,
    sounds like wrong design setup. Development board is using 125 MHz external oscillator as configuration clock, apparently you have selected internal oscillator as configuration clock in device options.

paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hello Madhur Juneja,


I’m glad that your question has been addressed, I now transition this thread to community support.

If you have a new question, feel free to open a new thread to get the support from Altera experts.

Otherwise, the community users will continue to help you on this thread.

Thank you.