Forum Discussion

mjuneja2007's avatar
mjuneja2007
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
Solved

Critical Warning while generating SOF file for CXLtype 3 example design

Hi, I am getting below Critical Warning while generating SOF file for the example design of CXL IP type 3 with DDR4 controller for Agilex-7 board (DK-DEV-AGI027-RA). "Message ID :- 24567 The desi...
Fpga Devkit
  • FvM's avatar
    FvM
    6 months ago

    Hi,
    sounds like wrong design setup. Development board is using 125 MHz external oscillator as configuration clock, apparently you have selected internal oscillator as configuration clock in device options.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
6 months ago

Hi,
sounds like wrong design setup. Development board is using 125 MHz external oscillator as configuration clock, apparently you have selected internal oscillator as configuration clock in device options.