Forum Discussion
New ContributorConstraining output clocks properly in *.SDC
Okay that makes sense. For now I'm using an eval board and this clock is not on a designated clock pin. When I compile it gives me a warning under Fmax "limit due to minimum port rate restriction" that it can only achieve up to 125MHz and we are running above that. In the final version, this pin will be routed on an actual clock pin.
Super ContributorYou'd need to check to see if the target device's PLL you are using is capable of whatever clock speed you are trying to generate. Perhaps it's too fast, causing the violation.
New ContributorOkay that makes sense. For now I'm using an eval board and this clock is not on a designated clock pin. When I compile it gives me a warning under Fmax "limit due to minimum port rate restriction" that it can only achieve up to 125MHz and we are running above that. In the final version, this pin will be routed on an actual clock pin.
