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Erica's avatar
Erica
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Constraining output clocks properly in *.SDC

Hi, I am generating a clock with a PLL that will also be driving an external device. I am using a clock buffer (altclkctrl) in between and wondering how to constrain it properly? I'm currently usin...
  • Erica's avatar
    Erica
    5 years ago

    Okay that makes sense. For now I'm using an eval board and this clock is not on a designated clock pin. When I compile it gives me a warning under Fmax "limit due to minimum port rate restriction" that it can only achieve up to 125MHz and we are running above that. In the final version, this pin will be routed on an actual clock pin.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

All clocks need to be constrained, no matter what resources are used. Your constraint for the output clock is correct. Add this

set_false_path -to [get_ports {SDRAM_OUT}]

so that the output clock path is not analyzed as a data path.

Erica's avatar
Erica
Icon for New Contributor rankNew Contributor
5 years ago

Okay perfect!

Thank you very much again,

Erica