i! I have my Arria10 custom board2x TSE-PHY MICREL-Ethernet Ports A,BA,B linked to PC NIC works fine (I send and transmit frames from PC to TSE and vice-versa) , I see 100 Mbps, Full Duplex, Auto MDI/MDI-X default enabled Connecting TSE A to B with same crossed cable already tested before, PHYs never goes up!!!! There is another manouvre to do to wakeup TSE-PHY???Thanks to everyone knows this question!

Hi, What is the Core variation of TSE that you selected? Do you perform any auto negotiation. Regards -SK

I'm using Quartus Prime 18.1. Autonegotiation is on on both TSE. Chip PHY is micrel KSZ9031MNX. I'm trying at 100 Mbps. I'm using a simple sw confioguration from Eclipse, written to read/write PHY registrer using MDIO interface on TSE, without problem. I can read/write all my PHY registersWith PC NIc Card : Link goes UP 100 Mb full-duiplex (cross cable, but runs with straight one due to MDI-X capabiliy)Connecting TSE A to B with same cross cable Link never goes UPSo, circuits and HW should be ok, PC NIC connection is stable... When connect TSE togheters, probably there is some actions at low network level that NIC PC card does and both TSE+PHY don't performs. I must discover what..... :-((I tried to connect TSE_A to TSE_A on MII internal side, inside FPGA and they runs fine with my frames applications.)If anyone knows this issue, I say thanks for any suggestion

Hi Based on my understanding, the FPGA only consist of MAC, where the PCS and PHY are external CHIP. The auto negotiation is occurring at the PCS level, I would suggest you to disable the auto negotiation, and fix the data rate at 100 Mb and see if it make any difference. Regards -SK

Nothiong to do.. if I fix speed both PHY doensnt' go UP and it is impossible to sending any thing. I tested them connecting to a D-link commercial 1Gb switch, limiting test to 100 mbps. They go up immediatly and I can sent/receive frames , no problem. Only when i connect one each other, PHY cannot go up. But should be possible connect 2 PHY each other, I think!!Another question... TSE MAC FILTERING seems don't run.. I set on TSE main control register TSE_PROMIS_EN=0 and TSE_CTRL_FRM_ENA=1 .. so TSE must receive only frames directed to it (MacD = Mac TSE) but it remains to receive any frame on user side.... !!!!!!If anyone has suggestions they are well accepted!! ThanksFilippo

Hi, If this is using external PHY (consist PCS and PMA), and the FPGA is only consist MAC, then I would suggest you to double check with the external PHY datasheet, and see if there is any setting required. I suspect the auto-negotiation is not success, and this is why i suggest to disable it, and see if it works. If you set PROMIS_EN = 0, and yes, it should filtering if the destination address does not match. What is the resisters mac_0 ,mac_1, and supplementary address that you configure? And what address that you receive but not filter? Did you try to do a software reset (SW_RESET)? Regards -SK

Connecting 2 TSE (with micrel PHY) each other: Link down

14 Replies

APaci1
Occasional Contributor
7 years ago
this is capture on avalon side, any frame with MAcD different from Primary MAC enter anyway... :-()
SengKok_L_Intel
Regular Contributor
7 years ago
For unicast address, bit 0 of the destination address is 0, but for your case the bit 0 is 1 (F). Could you please try the address below?
mac_0 = 0xccddeeff
mac_1 = 0x0000aabb
Or
mac_0 = 0x42E90700
mac_1 = 0x000028AC
APaci1
Occasional Contributor
7 years ago
Thnaks, I try set TSE_MAC Addr 0/1 and all secondary Macs to mac having 0 on lsbit as you suggest, but on avalon side results is the same, I receive all macs that arrives on this network segment... :-(
SengKok_L_Intel
Regular Contributor
7 years ago
I have run the simulation and confirm the address filtering is working fine from my site.
Could you please try the following setting, and read back the register to confirm?
Address 2 command_config = 0x048002b
Address 3 MAC_0 = 0x22334450
Address 4 MAC_1= 0x 0000EE11
Could you please also refer to the link below, section 5.3.1 and follow the recommended initialization sequences?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Forum Discussion

Connecting 2 TSE (with micrel PHY) each other: Link down

14 Replies

Recent Discussions

DK-DEV-AGI027RES Install Package

Why 390.625MHz clock to F-Tile Reference fequency

Cyclone V GT Dev Kit - new units fail to boot from FPP

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA