Connect External Arm DSTREAM Debugger and Arm Development Studio with Intel Stratix 10 SX DK

Hi Jingyang, Teh

Thanks a lot for the response. Essentially it seem like that the HPS JTAG is not visible to the debugger at all. This is what the SPL and U-Boot prompt looks like :

U-Boot SPL 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)
Reset state: Cold
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1105 ms
QSPI: Reference clock at 400000000 Hz
WDT:   Not found!
Trying to boot from MMC1


U-Boot 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)socfpga_stratix10, 6

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM:  4 GiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 9a:94:bf:47:78:41
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
SOCFPGA_STRATIX10 #

Do I need to deploy a different reference design to make HPS JTAG visible in the scan chain ? Any steps for configuring such a design ?