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Altera_Forum's avatar
Altera_Forum
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18 years ago

Configuring the Stratix2 device

Hi,

Am using stratix2 device in my design.

I have configured bank3 lines as LVDS inputs, however with this configuration am not able to program the device. I get the error nCE pin didn't go high as expected after programing. But if I use other banks without using LVDS i/o type am able to program the device.

nCE pin is connected to ground through a pull down resistor.

all the connections are also good as am able to load other designs.

Do I need to do any settings while using the LVDS pins?

Thanks n Regards,

Srikanth

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hii Srikanth,

    In ur .qsf file add this line and try to compile it once again.

    set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"

    and also try

    set_instance_assignment -name IO_STANDARD LVDS -to <name_port>

    Regards

    Sandeep
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    and one more thing Srikanth... can i know which Stratix II device ru using?

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Since when does Stratix II have LVDS on bank 3? LVDS channels are found on Banks 1,2,5, and 6.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    That is the reason I asked which device Srikanth is using.... boz LVDS is in banks 1,2,5 and 6 banks... Bank 3 is normal IOs.... I dint get any reply from him yet.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    Thanks for your time.

    Sorry for the wrong information. Its bank5. I tried by setting the unused pins to input tri-stated.

    But the problem seems to be something else. The design is using a single port ram and I enabled the option of using "In system memory content editor to read the contents of RAM" was not able to program the device.

    Then again compiled the design by disabling the above option then I was able to load the design into the device.

    But I need to read the contents of RAM during the run time! Is there any setting?

    Thanks n Regards

    Srikanth
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    Using In-System Memory Content Editor you should be able to read the content of the RAM once u configure the design into FPGA.

    In the 'JTAG Chain Configuration' on window select approprate Hardware and Device.

    In the In-System Memory Content Editor windown right click on the Device and click on

    Read Data from In-System Memory or Continiously Read Data from In-System Memory.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The following " To Customer " note was posted:

    " Hi Srikanth,

    Thanks for your prompt response.

    This is a known issue of the Stratix II devices. The solution was posted online at www.altera.com/support/kdb/solutions/rd01262005_186.html (http://www.altera.com/support/kdb/solutions/rd01262005_186.html) . Kindly please refer to the errata sheet Page 11, Table 7 at http://www.altera.com/literature/ds/esstx2fpga.pdf and follow the instruction recommended according to the device used.

    Hope that the information will resolve your inquiries. Kindly please get back to us if you still having any inquiries.

    Thanks for using mySupport.

    Best Regards,

    LF Hoe. "