Code for HC-06 works on ModelSim but not on DE2-115 Board

I manged to modify your code and eliminate some of the latch inferences as well as other issues. But I'm not sure if it would work, ie, functionally correct. The rest is upto you.. correct the functionality while sticking to the same coding guide.. for FSMs etc. Check with the simulation and see if it works.. As stated earlier, the HC-06 has a UART interface it would be easier to implement a UART and communicate with it.

module FYP (
  input wire        clk,
  input wire        rst,
  input wire        Rx,
  output reg [7:0]  RxData
 );
 
 reg        Tick;
 reg [11:0] Baud_counter;
 
 reg        RxDone;
 reg        RxEn;
 reg [4:0]  start_counter;
 reg        ReadEn;
 reg [4:0]  counter;
 reg [4:0]  Bit;
 reg [7:0]  Rx_Data;
 reg        Rx_Done;
 reg [4:0]  holdCounter;
 reg        holdDone;
 reg        holdEn;
 
 //State variables for FSM
 reg [1:0]  State; 
 parameter  IDLE = 0, READ = 1;
 
 reg [1:0]  holdSTATE;
 parameter  HOLD = 0, RELEASE = 1;
 
 
 always @(posedge clk or negedge rst) begin //setting tick at 16 times of Baud Rate 9600
   if (!rst) begin
	  Baud_counter <= 11'b0;
	  Tick         <= 1'b0;
	end
   else begin
     if (Baud_counter < 325)  begin 
		  Baud_counter <= Baud_counter + 1'b1;
		  Tick         <= 1'b0;
	  end
    else begin 
		  Baud_counter <= 11'b0;
		  Tick         <= 1'b1;
	 end
  end // else
 end//always
 
 
 always @(posedge clk or negedge rst) begin
 if (!rst) begin
   start_counter <= 5'b0;
	ReadEn        <= 1'b0;
 end
 else begin
   if (RxEn == 1'b1 && start_counter < 8 )	begin 
	  	  start_counter <= start_counter + 1'b1;
		  ReadEn        <= 1'b0;
   end
   else begin 
     if (RxDone == 1'b1) begin 
         start_counter <= 5'b0;
		   ReadEn        <= 1'b0;
	  end
	  else begin 
		 start_counter <= start_counter;
		 ReadEn        <= 1'b1;
	  end
	end
 end
 end//always
 
 
 always @(posedge clk or negedge rst) begin
   if (!rst) begin
	   State <= IDLE;
	end
	else begin 
     case (State)
	    IDLE: if (Rx==0) State <= READ;
		  	    else       State <= IDLE;
 	    READ: if (RxDone==1) 	State <= IDLE;
		   	  else 				State <= READ;
	    default: State <= IDLE;
     endcase
   end //else
end //always
 
 
always@(State) begin
  case (State)
	  READ: RxEn <= 1'b1;
	  IDLE: RxEn <= 1'b0;
	  default: RxEn <= 1'b0;
  endcase 
end //always
 
always @(posedge Tick or negedge rst) begin
  if (!rst) begin
    counter <= 0;
	 Rx_Done <= 1'b0;
	 Bit     <= 1'b0;
	 Rx_Data <= 8'b0;
  end
  else begin 
    if (ReadEn==1) begin 
      if (Bit<8) begin 
			if (counter<16) begin 
					counter <= counter + 1'b1;
					Rx_Done <= 0;
					Bit <= Bit;
			end
			else begin 
			   	counter <= 0;
					Rx_Done <= 0;
					Rx_Data <= {Rx,Rx_Data[7:1]};
					Bit <= Bit + 1'b1;
			end //(counter<16)
		end //(Bit <8)
      else begin 
		  counter <= 0;
		  Bit <= 0;
		  Rx_Done <= 1;
      end
    end //(ReadEn)
  end
end
 
 always@(posedge clk or negedge rst) begin
 if (!rst) holdSTATE <= RELEASE;
 else begin
   case (holdSTATE)
	  RELEASE: if(Rx_Done==1) holdSTATE <= HOLD;
		  	     else 			  holdSTATE <= RELEASE;
		
	  HOLD   : if(holdDone==1) 	holdSTATE <= RELEASE;
			     else   				holdSTATE <= HOLD;
	  default: holdSTATE <= RELEASE;
	endcase 
 end
end //always
 
always @(holdSTATE) begin
  case (holdSTATE)
	  RELEASE: holdEn <= 1'b0;
	  HOLD   : holdEn <= 1'b1;
	default  : holdEn <= 1'b0;
  endcase
end //always
 
always @(posedge clk or negedge rst) begin
  if(!rst) begin
 		holdCounter <= 0;
		holdDone    <= 0;
		RxDone      <= 0;
  end
  else begin
    if (holdEn==1 && holdCounter<10) begin 
        holdCounter <= holdCounter + 1'b1;
        RxDone      <= 1'b1;
        holdDone    <= 0;
	 end
	 else begin 
		holdCounter <= 0;
		RxDone      <= 0;
		holdDone    <= 1'b1;
	 end
	end
end //always
 
always @(posedge Tick) begin
  if(RxDone==1) RxData = Rx_Data;
  else          RxData = RxData;
end
endmodule