Forum Discussion
From the datasheet of the HC06 Bluetooth device, it looks like the Tx and Rx ports are UART compatible ports. In this case, I would suggest you interface these ports to an UART in the FPGA. There are simple UART implementations that you can get on the internet or from the Intel FPGA IP in Quartus. This would simplify the data transfer between the HC06 device and FPGA.
Looking at your code, there are a lot of issues, lots of latch-inference is taking place and this is not good for RTL/FPGA design. We try not to infer latches as much as possible since it would result in timing issues. I would suggest you use a reset signal to set the Flops in the design to a known state. Also make sure you are encoding and designing the FSM correctly so as to not infer latches and unwanted logic.