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Altera_Forum
Honored Contributor
Honored ContributorClock signal in De2-115
I am using DE2-115 development board. I have written a verilog code where I am trying to generate a sequence of 1' and 0's using the clock frequency of 50MHz and I am getting the output as shown in t...
Altera_ForumHonored Contributor
Honored ContributorI imagine it also has something to do with the speed of the IO transistors. I do not know what the slew rate of these transistors is, but someone else might know. Try looking at each clock on the same division settings. I think you will see each edge has about the same slope.
