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PShetty's avatar
PShetty
Icon for New Contributor rankNew Contributor
7 years ago

Clock sharing between the Arria 10 Transceiver Banks

Hi, We have Arria 10 SoC design,where we are using 4 high speed transceiver channels from each bank(1E,1F,1C,1D) . 4 Transceiver PHY IPs are used to configure the 4 channels from each banks. My ques...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, I am not aware of any specific restriction on this. However, it is recommended for you to run through Fitter compilation, and then check if there is any warning related to the refclk placement or driving distance. Thank you. Best regards, Chee Pin