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Akshay_A's avatar
Akshay_A
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9 months ago

Clock Selection Issue with PHYLite IP in DDR Data Capture

I am working on a design where I need to delay calibrating incoming DDR data from an external source and sample the same data to convert it to SDR. To achieve this, I am using the PHYLite IP, whic...
Fpga Devkit
Zehui's avatar
Zehui
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8 months ago

Hello,

Apologies for the late response.

Unfortunately there is no way to bypass this restriction. group_0_strobe_in must be coming from an external source. The strobe feature of PHY Lite IP is associated with some hardened resources and there is no path for an internal clock to reach these resources.

Thanks.