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Altera_Forum's avatar
Altera_Forum
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10 years ago

Clock generator on DE0-Nano-SoC

The Terasic DE0-Nano-SoC contains a programmable clock generator (CDCE937) which is controllable from I2C. The bundled example GHRD design has conditional FPGA port definitions (CLK_I2C_SDA/SCL), but...
GAnic's avatar
GAnic
Icon for New Contributor rankNew Contributor
6 years ago

Actually the pins are connected and you can reprogram the CDCE937 chip through I2C from the FPGA, the existing configuration uses only the PLL1 and PLL2 to create all frequencies so you can program the PLL3 to get an arbitrary frequency on the FPGA_CLK2 pin for example. The connections to the FPGA are SDA=AA4 and SCL=U10, the address of the chip is the default (as noted in the schematics)

The default configuration (registers 0x00-0x3f) is as follows:

A1 01 34 01 02 50 80 00 00 00 00 00 00 00 00 00 00 00 00 00 4D 02 08 00 FE BA 32 07 00 40 02 08 00 00 00 00 0D 02 04 00 FE BA 32 07 00 40 02 08 00 00 00 00 8D 02 00 00 6A 4A A3 4C 00 40 02 08