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AGlad5's avatar
AGlad5
Icon for New Contributor rankNew Contributor
6 years ago

clarification in virtual jtag communication

We have made a design with a virtual jtag instance for a Stratix 10 FPGA. While performing virtual dr shifts we have been seeing unexpected instant feeback behavoir. It seems as though the dr shift i...
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi AGlad5,

It has been a while since you have posted an update to this Case. Do you have any latest update?

Can I say this issue is no longer an issue now?

Thanks.

Regards,

Matt

Regards,

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