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Altera_Forum
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18 years ago

CII DSP kit audio examples using DSP Builder

I made a sample driver for TLV320AIC23 Stereo Audio CODEC chip which is mounted on CII DSP kits in Verilog-HDL. I attach the files with two very simple DSP Builder projects. sound_basic_dspb\sound...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi EOFZ,

I have downloaded and use your excellent codec interface files.

It works properly on EP2S60 DK and all I had to do was pins assignment.

I analyzed your code and simulink model .

I don't understand the logics of synchronizing clocks.

BCLK = 40MHz /16 and SCLK 40MHz/32 .

Following your registers mapping the interface works in USB clock mode i.e. 12MHz .

After I changed Sample Rate Control Register to 8 Khz input and output the results I received were the cut off 6KHz which means 12Khz sample rate.

I'll really appreciate your help.

yan_w