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JDali1's avatar
JDali1
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6 years ago

Channels mix-up with DE10-Nano ADC IP (the IP from Quartus IP Catalog for hardware only design, not the one from Platform Designer IP Catalog with Avalon-MM interface)

Trying to use University Program IP from Quartus IP Catalog to interface ADC on a DE10-Nano board (altera_up_avalon_adv_mega), I found that channels are not routed correctly from connector to IP outp...
JDali1's avatar
JDali1
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6 years ago

Hello Anand,

Thanks for you answer.

I generated a new IP variation with default parameters (ADC clock = 12.5MHz / 8 channels / system clock = 50Mhz) and repeated the test. This time everything is fine, no mix-up, so maybe there is some timing issue at max speed on the DE10-Nano.

As I would need to use ADC at max frequency for my project, I will repeat the test to find max possible frequency without issue. In the mean time any advise is welcome!

Regards,

Jean-Guilhem