Forum Discussion

JDali1's avatar
JDali1
Icon for New Contributor rankNew Contributor
6 years ago

Channels mix-up with DE10-Nano ADC IP (the IP from Quartus IP Catalog for hardware only design, not the one from Platform Designer IP Catalog with Avalon-MM interface)

Trying to use University Program IP from Quartus IP Catalog to interface ADC on a DE10-Nano board (altera_up_avalon_adv_mega), I found that channels are not routed correctly from connector to IP outp...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Jean,

Can you check again using RTL viewer? It looks fine.

All ADC_IN channels are rooted correctly using mux.

There is no mix up in SW/select line or data/ ADC_IN.

Regards

Anand

Recent Discussions