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AmirKhan's avatar
AmirKhan
Icon for New Contributor rankNew Contributor
2 years ago
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Changing VCCIO voltages in DE0-Nano board

Hi, I need to test my ASIC which takes 1.2V and 3.3.V. I have designed my PCB without knowing much about the banks of FPGA. It certainly implies that I am a newbie in FPGA. I can manage this by cha...
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Fpga Devkit
  • FvM's avatar
    FvM
    2 years ago
    DE0-Nano manual and schematic drawing should be your first reference. It clarifies that all VCCIO pins are connected to 3.3V rail. Whatever you declare in pin planner, real VCCIO will be 3.3V.

    Although officially unsupported, you can assign 2.5 V to a bank and use LVDS receivers, at least at reduced performance.
AmirKhan's avatar
AmirKhan
Icon for New Contributor rankNew Contributor
2 years ago

Thanks for your prompt reply.

The Cyclone IV E supports all supply voltages. It means that FPGA supports but not the board. I have seen this in Cyclone IV device handbook. One more thing, in the settings (as shown in image attached), it shows multiple options for selection but they are disabled. Is it restricted by the Device type i.e. other boards support such allocations? If yes, then please let me know name of such boards.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
The screenshot doesn't show multiple options. All FPGA voltages except VCCIO are fixed.

VCCIOx are usually hardwired by board design, in some cases jumper or even electronically selectable.
Many development boards have some banks connected to 2.5 V to support LVDS interfaces, some have 1.8 or 1.5 V banks for newer DDR RAM types.