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Altera_Forum
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11 years ago

Can't create workable controller for SRAM 512 kb (ISSI IS61LV25616AL) on Altera DE1

Hello all.

I have a problem with SRAM 512 kb (ISSI IS61LV25616AL) on Altera DE1.

My problem is:

If i set memory address and writing data to memory cell with this address, after if i change address to another address i read last data from that address (which was writed on last adress). And if i change address again, i read this last writed data. I read last writed data from all adresses.

I writed more simple verilog sram controller (OE CE UB LB is always 0). And i change only WE for control read and write.

But i have same problems. I read last writed data from all adresses

qar file in attachement.

Thanks in advance for any help

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    problem is solved.

    We have 16 bidireсtional pins for data writing/reading on SRAM 512 kb (ISSI IS61LV25616AL) on Altera DE1.

    And I define this 16 pins as "reg" type with "inout" direction in my verilog module: 

    
module new_simple_controller
	(
		...
		inout reg  data_bidir,
     		...		
		
	);

    But as I think - "reg" type can change value only inside verilog module. And this value can't be changed from outside.

    When I writed data to SRAM, this data writed to "reg". But when I readed data from SRAM, i only readed previous writed data from "reg" (but not data which readed from SRAM).

    Thanks to Shawn Gerber (http://www.youtube.com/watch?v=ubsreeqe8hw&list=uu2tvyj0h_2txv9oxqeha7uq - SRAM Controller in Verilog for Altera DE1 board). He sended me source code of his SRAM controller and I finded this mistake in my code.

    solution of this problem is following:

    1) "Inout" direction for 16 SRAM data pins only "wire" type. 

    
module controller_for_sram_is61lv25616al
	(
	   	...
		
		inout wire  data_from_to_sram_input_output,
		
		...
	
	);

    2) Add three registers. 

    
reg  register_for_reading_data; // intermediate buffer register for reading data
reg  register_for_writing_data; // intermediate buffer register for writing data
   
reg register_for_splitting; // register for disabling last "assign"
// if = 0 - disable last "assign" (switch last "assign" to high impedance state)
// (when we read data from bidirectional SRAM port - we can't write dada to this port)
// if = 1 - enable last "assign"
// (when we write data from intermediate buffer register "register_for_writing_data" to bidirectional port)

    3) Reading from SRAM. 

    
register_for_reading_data<=data_from_to_sram_input_output; // we read data, when last "assign" in high impedance state

    4) Writing to SRAM. 

    
assign data_from_to_sram_input_output = (register_for_splitting) ? register_for_writing_data : 16'bz; // last "assign"

    Controller source code (controller_for_sram_is61lv25616al.v) and diagram of work (diagram_of_work.pdf) in attachment.