n-slipstream
New Contributor
3 years agoCannot Convert RAM Megafunctions with Max 10
Synthesis Error:
Info (276014): Found 1 instances of uninferred RAM logic Info (276013): RAM logic "Datapath:Datapath|RAM_AD9914_0:RAM_AD9914_0|ram_instance" is uninferred because MIF is not supported for the selected family Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis
If I change the project to use 'Single Compressed Image with Memory Initialisation' it builds fine but I must use 'Dual Compressed Images' as this will be a RSU (remote system upgrade) project.
It looks like this is the cause when the ram is defined:
Is there an alternative way to achieve this
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use WORK.COMMON.ALL; entity RAM_DAC is generic ( NUM_OF_REGISTERS : natural := 1023; -- Number of registers containing data to send on SPI ADDR_WIDTH : natural := 10; DATA_SIZE : natural := 12); -- 12 bit word sets analog output Port ( CLK : in STD_LOGIC; WriteEn : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (11 downto 0); Address : in UNSIGNED (ADDR_WIDTH-1 downto 0); WR_ADDR : IN UNSIGNED (ADDR_WIDTH-1 downto 0); FRAME_SIZE : in STD_LOGIC_VECTOR (15 downto 0); DataOut : out STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0) ); end RAM_DAC; architecture Behavioral of RAM_DAC is -- Declare memory parameters type ram_type is array (0 to NUM_OF_REGISTERS) of STD_LOGIC_VECTOR(DATA_SIZE-1 downto 0); signal ram_instance: ram_type := ( 0 => "100000000000", 1 => "100000000000", -- bit pattern 1000 0000 0000 is 0V on the DAC output, this is the preferred default output 2 => "100000000000", 3 => "100000000000", 4 => "100000000000", 5 => "100000000000", 6 => "100000000000",