New Contributor
Regular ContributorHi,
- Can you provide numerical data - or some sort of report of your testing ?
Unfortunately we do not have the number or data for it. The reason is that not all CRC error is critical. Let say if the SEU is happening on the location that does not have any function then you are safe to continue what you are performing as it is not impacting the device. What we are performing is only to make sure that if there is any real SEU is happening then will the CRC error been triggered. So the testing that has been performed will not be showing the real result as it will depend on when CRAM bit is being attack.
- Can you elaborate on the statement to the error detection capability of the CRC circuit ?
I understand your concern. But if all the bit is changed then the CRC signature will also be mismatch and it will be flag as multiple bit error. So most importantly when we performed SEU error and you are observing functionality failure then we recommend that you need to recover from the SEU as it has already impacted the CRAM bit of your design on the Cyclone IV/V series device. For the higher end device which has the capability to isolate the exact location and determine if this is critical bit or not then you will need to based on this information rather than only CRC_Error signal. The reason is that if the issue is happening on non-critical bit area then I would recommend you to continue the functionality of the device as it will not impact anything.
The SEU is able to detect it but not able to fully detect which bits is located when it is occurring on multiple bit error for Cyclone IV/V series.
If you look into AN866 (https://www.intel.com/content/www/us/en/programmable/documentation/drj1530911544883.html) in chapter - SEU FIT Parameters Report, we are providing you the report of the the SEU occurring based on your design rather than taking account of the full FPGA. The reason is that we do not want to trigger a false alarm when the SEU is happening on the unused logic.
