Forum Discussion
SKacc
New Contributor
New ContributorCan we able to operate system clock of FPGA with 25MHz or 50MHz input?
Arria V Device Overview(AV-51001) says the input reference clock ranges from 27MHz to 710MHz.
AnandRaj_S_Intel
Regular Contributor
Regular ContributorHi Srikanth,
Yes, you can have a 25 MHz or 50 MHz system/global clock for FPGA. And use PLL to generate the required clock frequency for other design modules (ddr/transceivers/ADC).
Refer respective datasheet under the clock-tree session.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand
SKaccDatasheet says global or regional clock frequency is either 625 or 525 MHz only. (Document ref: AV_51002, Page No 44).
