Can we able to operate system clock of FPGA with 25MHz or 50MHz input?

Hi Srikanth,

Yes, you can have a 25 MHz or 50 MHz system/global clock for FPGA. And use PLL to generate the required clock frequency for other design modules (ddr/transceivers/ADC).

Refer respective datasheet under the clock-tree session.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand