Forum Discussion
6 Replies
- ophied
New Contributor
My apologies -- I was actually confused earlier about how this example outputted it's signals (for some reason I thought it would output them as A/B/C/D differential pairs, but it clearly does not) -- I think you're right that this is applicable to what I'm doing and I'm currently trying to implement it.
I think my issue might have to do with timing, but with this HPS-to-FPGA setup I can play with delays on the rx and/or tx clock lines and maybe get it to work.
- aikeu
Regular Contributor
Hi ophied,
Are you using a Cyclone V custom board?
There is an design example that which might help:
https://www.rocketboards.org/foswiki/Projects/CycloneVRGMIIExampleDesign
Thanks.
Regards,
Aik Eu
- ophied
New Contributor
It is a custom board -- I have the single-ended RGMII I/Os routed to a KSZ9897R switch IC, specifically port 7 of the switch, which is a MAC interface port.
Thanks for the link, although I've seen and reviewed this example before. The FPGA IP's that are used ("HPS EMAC Interface Splitter Core" which feeds into the "GMII to RGMII Adapter Core" IP) actually only output differential PHY RGMII signals, so it's not something I can use in my design's MAC to MAC configuration.
- aikeu
Regular Contributor
- aikeu
Regular Contributor
Hi ophied,
I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Do give good survey feedback if receive any.
Thanks.
Regards,
Aik Eu