Can LVDS clock pin be assigned to general differential IO?

Here is the example module instantiate LVDS:

module top (

input lvds_clk_in,

output lvds_clk_out,

input lvds_rx_in,

output lvds_tx_out

);

lvds_rx lvds_rx_inst (

.rx_inclock (lvds_clk_in), // rx_inclock.rx_inclock

.rx_in (lvds_rx_in), // rx_in.rx_in

.rx_out (lvds_rx_data), // rx_out.rx_out

.rx_data_align (bit_slip_sync2), // rx_data_align.rx_data_align

.rx_outclock (rx_outclock), // rx_outclock.rx_outclock

.pll_areset (!lvds_rstn), // pll_areset.pll_areset

.rx_locked (rx_locked) // rx_locked.rx_locked

);

lvds_tx lvds_tx_inst (

.tx_in (lvds_tx_data), // tx_in.tx_in

.tx_out (lvds_tx_out), // tx_out.tx_out

.tx_outclock (lvds_clk_out), // tx_outclock.tx_outclock

.tx_coreclock (tx_coreclock), // tx_coreclock.tx_coreclock

.tx_inclock (clk_100_max10), // tx_inclock.tx_inclock

.pll_areset (!lvds_rstn), // pll_areset.pll_areset

.tx_locked (tx_locked)

);

endmodule

Here is pin assignment with Good/Bad assign, Device : 10M50DAF484C6GES

#hsmc_clk_in =============== Good Pin assignment

set_location_assignment PIN_V10 -to lvds_clk_in

set_location_assignment PIN_V9 -to lvds_clk_in(n)

#hsmc_clk_in =============== Bad Pin assignment

#set_location_assignment PIN_W6 -to lvds_clk_in

#set_location_assignment PIN_W5 -to lvds_clk_in(n)

#hsmc_clk_out

set_location_assignment PIN_W8 -to lvds_clk_out

set_location_assignment PIN_W7 -to lvds_clk_out(n)

#hsmc_rx

set_location_assignment PIN_V5 -to lvds_rx_in

set_location_assignment PIN_V4 -to lvds_rx_in(n)

#hsmc_tx

set_location_assignment PIN_W3 -to lvds_tx_out

set_location_assignment PIN_W4 -to lvds_tx_out(n)