Can ARM timing be corrupted?

1) Are you using our Intel board? Try to use our example design and make sure it works on the Intel board. From there you can make the comparison on the DDR settings. 2) It can be either connection, clock, or held in reset issue with the EMIF. Try to read any address related to ‘ecc_hmc_ocp_slv_block’. Also, check with your HW team to verify whether your DDR calibration fine by using the DDR toolkit (remove hps component and replace it with emif block) 3) Or use the same Uboot binary elf image (different devicetree blob) and run it on the A10 Soc board that you have. Check whether your DDR cal passes and boots to console promt? 4) If you have calibration failure, check your DDR PLL reference clock on the board matches the frequency specified in the Qsys? If that clock is fine and free running, you can also find the I/O PLL locked signal in signaltap and confirm that it’s locked. 5) check DDR RefClock is in the stable condition where it is not under load?