Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi,
I've got something new. In SOPC I add an onchip memory named onchip_ssram (@ auto assigned at 0x00080000 to 0x00098fff). I connect this memory to instruction master and data master (nios) and sgdma_rx.m_write and sgdma_tx.m_read. I set in cpu, exception adresse to onchip_ssram + offset 0x120. Build it, compile. Go to SBT refresh, generate BSP and debug. The program start but break at : alt_u8 alt_avalon_sgdma_do_sync_transfer( alt_sgdma_dev *dev, alt_sgdma_descriptor *desc) … … … … … /* Wait for the descriptor (chain) to complete */ while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(dev->base) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) ); … … in the file altera_avalon_sgdma.c It wait for sgdma not busy ??? Someone got an explication or idea. Thanks.