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GuilleJake's avatar
GuilleJake
Icon for New Contributor rankNew Contributor
4 years ago
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BURST ACCESS with UNIPHY DDR-FPGA and DDR-HPS memory controller in CYCLONE V, using QUARTUS Prime 18

WRITE BURSTS Since the beginbursttransfer signal no longer exists, if you want to concatenate successive write bursts: Q: is it necessary to enter a dead cycle with write=0 at the end of each bur...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi GuilleJake,

    The controller can identify the burst operation from user's command.

    When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.

    So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.

    Then the controller will act accordingly to do the burst operation.

    They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.

    Thanks,

    Adzim

GuilleJake's avatar
GuilleJake
Icon for New Contributor rankNew Contributor
4 years ago

Dear Adzim

Your phrase "The Figure 15 in Avalon Interface Specification document has shown the contiguous read burst operation." is a perfect way to explain my question. In this figure two master nest two burst read requests ... but using beginbursttransfer to insert each request. Since beginbursttransfer is not available any more as an Avalon signal ....

How should these two master make the same operation WITHOUT having beginbursttransfer available?

How does the memory controller know that the masters want to insert a bursttransfer request?

Is the task of beginbursttransfer now replaced by the activation of "read" signal alone (with burstcount /= 1 to signal that it is a burst read request)?

Thanks

Guillermo

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi GuilleJake,

The controller can identify the burst operation from user's command.

When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.

So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.

Then the controller will act accordingly to do the burst operation.

They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.

Thanks,

Adzim