Forum Discussion
New ContributorBURST ACCESS with UNIPHY DDR-FPGA and DDR-HPS memory controller in CYCLONE V, using QUARTUS Prime 18
Hi GuilleJake,
The controller can identify the burst operation from user's command.
When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.
So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.
Then the controller will act accordingly to do the burst operation.
They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.
Thanks,
Adzim
Regular ContributorHi GuilleJack,
The memory controller can perform the burst operation without the beginbursttransfer signal.
When you assign a command to perform the burst operation, the controller knows when to start the operation.
For your read burst questions, you are right for both read burst operations.
The Figure 15 in Avalon Interface Specification document has shown the contiguous read burst operation.
The amount of the commands that can be held is set in the Starvation limit for each command in the EMIF IP.
You can find it in the Controller Settings under the Efficiency section.
The limit is at 63 commands.
Thanks,
Adzim
