Forum Discussion
New ContributorBURST ACCESS with UNIPHY DDR-FPGA and DDR-HPS memory controller in CYCLONE V, using QUARTUS Prime 18
Hi GuilleJake,
The controller can identify the burst operation from user's command.
When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.
So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.
Then the controller will act accordingly to do the burst operation.
They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.
Thanks,
Adzim
New ContributorDear Adzim
If you look carefully at my original post I've made 5 questions, all related to management of contiguous burts, and about the need (or not) of inserting dead cycles in between (in my application I have to transfer blocks of 200 Mbytes at maximum speed to DDR-FPGA external DDR3 RAM). Your answer didn't give any response, you`ve sent me to read the databooks (thing I obviously made BEFORE asking here) and a formula about burstcount that is not related to my questions. Obviously the ticket stays open, I'm yet waiting for an effective answer. I'm not an FPGA beginner, I've been ALTERA FAE for ARROW Latin America for 15 years, and I've been in charge of ALTERA University Program for Spanish speaking countries for near two decades (Ralene Marcocchia's gold era) teaching about FPGA Design everywhere, from Mexico and Spain to Argentina.
- GuilleJake
Dear Adzim
Your phrase "The Figure 15 in Avalon Interface Specification document has shown the contiguous read burst operation." is a perfect way to explain my question. In this figure two master nest two burst read requests ... but using beginbursttransfer to insert each request. Since beginbursttransfer is not available any more as an Avalon signal ....
How should these two master make the same operation WITHOUT having beginbursttransfer available?
How does the memory controller know that the masters want to insert a bursttransfer request?
Is the task of beginbursttransfer now replaced by the activation of "read" signal alone (with burstcount /= 1 to signal that it is a burst read request)?
Thanks
Guillermo
- AdzimZM_Altera
Regular Contributor
Hi GuilleJake,
The controller can identify the burst operation from user's command.
When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.
So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.
Then the controller will act accordingly to do the burst operation.
They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.
Thanks,
Adzim
