BURST ACCESS with UNIPHY DDR-FPGA and DDR-HPS memory controller in CYCLONE V, using QUARTUS Prime 18

Hi GuilleJake,

The controller can identify the burst operation from user's command.

When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.

So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.

Then the controller will act accordingly to do the burst operation.

They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.

Thanks,

Adzim