BeMicro FPGA-based MCU Evaluation Board

I generally agree. A special point is, that BeMicro has been designed by Hitex, using a form factor they had introduced for other evaluation boards (e.g. NXP ARM) before. I don't know, if it's an Altera contract development at all.

The I/O connector mapping is completely documented in the BeMicro manual, for the FT2232 connection I have posted my findings in another thread:

http://www.alteraforum.com/forum/showthread.php?t=20490

In addition, here are the FT2232 connections

AD0	TCK
AD1	TDI
AD2	TDO
AD3	TMS
AD4	NCONFIG
AD5	NSTATUS
	
AD6	CONF_DONE
	
AC0	4052 Sel A
AC1	4052 Sel B

The 4052 is multiplexing the FT2232 JTAG pins according to Sel A/B as follows:

	0	1	2	   3
TMS	NC	IO	NC	   R404/TMS
TDO	NC	IO	NC	   R406/TDO
TDI	NC	IO	DATA	   R403/TDI
TCK	NC	IO	R402/DCLK	R401/TCK

I didn't have a need to trace the FPGA I/O pins connected in Select 1 mode. Select 3 is the default mode used for JTAG configuration.