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Altera_Forum's avatar
Altera_Forum
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16 years ago

BeMicro FPGA-based MCU Evaluation Board

This is the new BeMicro FPGA-based MCU Evaluation Board thread. Please post your questions and comments within this thread. Documentation and purchasing information can be found at www.arrow.com/bemi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi,

Error: Can't generate netlist output files because the file C:/altera/kits/bemicro/bemicro_sopc_builder_lab/incremental_db/compiled_partitions/bemicro_lab_schem.root_partition.map.atm" is an OpenCore Plus time-limited file

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You don't need the netlist to complete the lab. As long as you get the time limited file to generate, then you are good to go.