Beginners question: Debugging a FPGA design on an Altera Board

And here we go again...

In the test design I created to play around with Qsys I needed an AXI master interface exported to the entity of the component. I tried every AXI component available in Qsys. But the only component offering an AXI master interface that can be exported is a streaming component (Altera Axi Slave Agent) and I cannot connect this component to the Avalon MM Pipeline bridge. I also tried to add one of the available streaming interfaces but they have two streaming ports (read_cp and write_cp) and I can connect only one to the bridge.

In my test design I finally ended up with importing my AXI slave component into Qsys. Then I connected the AXI slave interface to the Avalon MM bridge. So I got a workaround for this problem. But is there any way to export an AXI master interface to my Qsys component that is connected to the Avalon MM Bridge? Basically I want this:

| USB Debug Master <=> Avalon MM Bridge <=> AXI Master Interface (exported) | <=> My component outside of Qsys with AXI slave interface