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Altera_Forum
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12 years ago

Beginners question: Debugging a FPGA design on an Altera Board

Hi everybody. I'm new to this board and to Altera development boards. And I have a question which probably has already been answered 1000 times in the past but I could not really find anything using ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I think QSYS will automatically insert the right components to connect an Avalon MM master to an AXI slave. The slave agent component (with the streaming interfaces) is one of the components which is inserted by QSYS to do this.

Are you able to connect the USB debug master to your slave in the patch panel?

If you want to simulate (eg in Modelsim) then the JTAG Avalon Master component in 13.1 has simulation support so in your simulated design you can replace the USB Debug Master with this. The two components are equivalent functionally, but the USB debug master is quite a lot faster in hardware.