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Altera_Forum's avatar
Altera_Forum
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14 years ago

BCLK on WM8731

Hi , I am trying to grab incoming ADC data and also sending out data to DAC on WM8731. Now the datasheet says the max clk for bclk is 20Mhz , and the toggle btw L and R channel should be 1/fs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

it seems I was wrong above. I copy from the datasheet:

"in slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-spaace ratio. BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC/ADCLRC transition to clock the chosen data word length..."

So, ADCLRC doesn't need to be fixed...

cheers

g