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Altera_Forum's avatar
Altera_Forum
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14 years ago

BCLK on WM8731

Hi , I am trying to grab incoming ADC data and also sending out data to DAC on WM8731. Now the datasheet says the max clk for bclk is 20Mhz , and the toggle btw L and R channel should be 1/fs...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I just wanted to add that i have set the sampling rate for the ADC and DAC to be 48Khz , actually i am following the neuron_audio_codec example . But what i dont understand that the datasheet mentions that the max BCLK can go up to 20MHz but it does not mention the min range , what if i want to run BCLK at 40khz will it still spit out data at 40Khz serially? :(

well technically it is not possible since WM8731 dosent have a any memory storage or buffering resurces ,:confused:

And yes the question of ADCLRC signal time period is dependent on what BCLK is since ADCLRC signal has to be high for 16 clock pulses of BCLK .