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Altera_Forum
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10 years ago

Basic Question aout I/O Pins on MAXII

Hi guys! I'm relatively new to FPGA's and CPLD's. I have successfully used and programmed a Cyclone V dev board in university, so i understand the basic principles of Quartus 2. Now I wanted ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Adrian,

By default the bdf file that you have created will be auto-assigned as top level design file. You would not need to create the top level again at the pin planner.