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Altera_Forum
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17 years ago

Audio CODEC AIC23 vhdl/verilog

Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any contro...
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Altera_Forum
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16 years ago

Your design tries to implement both asynchronous set and reset for stop_flag, which isn't provided with Cyclone III. The intended asynchronous set at power up (initial value) is ignored. Check, if you can change the initial value. If not, modify the design.