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Honored Contributor
Honored ContributorAudio CODEC AIC23 vhdl/verilog
Hello, We have a Altera EP2S60 development board (http://www.altera.com/products/devkits/altera/kit-dsp-2s60.html) , which has a Stratix II FPGA and AIC23 Audio CODEC. Altera does not have any contro...
Altera_ForumHonored Contributor
Honored ContributorHi EOFZ,
"Time requirement not met " is solved. but i face Critical Warning: Ignored Power-Up Level option on the following registers Critical Warning: Register command_gen:u_command_gen|stop_flag will power up to Low. How can i solve this problem? I using Cyclone III. tks.
