Forum Discussion
Occasional ContributorAssignment Inconsistent with Chip planner
Regular ContributorHi,
Can you provide the test case and steps to reproduce the error?
Thanks.
Best regards,
KhaiY
Occasional ContributorHi KhaiY,
Thank you for your concern!
It seems that we meet agian, and you helped me with the topic "Ignored Buffers in Delay Line Design" before.
This is a continued version from that one and here I have attached the updated archieved project for your reference again.
After running "fitter" of the compile stage, a combinational circuit "delay_out" is found in resource editor at the location FF_X10_Y19_N17, whereas we expect to see a flip flop.
This is the most confusing part and I do not know why this happens. All location assignments are in the txt file of my previous attachment "Assignment_inconsistency".
Could you please help me with this?
Thank you!
Mingqiang
- KhaiChein_Y_Intel
Hi Mingqiang,
If you refer to the Technology Map Viewer, the input of detector is connected to an output of a com binational logic named delay_out.
When you locate in Resource Property Editor, you will see the connectivity between the delay_out and detector. The location for the detector is corect, which is FF_X10_Y19_N17.
Please let me know if you have any questions.
Thanks.
Best regards,
KhaiY
- KhaiChein_Y_Intel
Hi Mingqiang,
Sure. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best regards,
KhaiY
